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Projects List of VLSI

  1. An Efficient TCAM-Based Implementation of Multipattern Matching Using Covered State Encoding (IEEE 2012)
  2. Block Recombination Approach for Subquadratic Space Complexity Binary Field Multiplication Based on Toeplitz Matrix-Vector Product (IEEE 2012)
  3. High-Speed Architectures for Multiplication Using Reordered Normal Basis (IEEE 2012)
  4. FFT Implementation with Fused Floating-Point Operations (IEEE 2012)
  5. Efficient Majority Logic Fault Detection With Difference-Set Codes for Memory Applications (IEEE 2012)
  6. Design and Implementation of Low Power Clock Distribution Network(IEEE 2012)
  7. Nonbinary LDPC Code Decoder Architecture With Efficient Check Node Processing(IEEE 2012)
  8. A Simple Circuit Approach to Reduce Delay Variations in Domino Logic Gates(IEEE 2012)
  9. Implementation of VLSI-Oriented FELICS Algorithm Using Pseudo Dual-Port RAM(IEEE 2012)
  10. Area-Efficient VLSI Implementation for Parallel Linear-Phase FIR Digital Filters of Odd Length Based on Fast FIR Algorithm(IEEE 2012)
  11. A High-Performance Energy-Efficient Architecture for FIR Adaptive Filter based on New Distributed Arithmetic Formulation of Block LMS Algorithm(IEEE 2012)
  12. A Novel Interpolation Chip for Real-Time Multimedia Applications(IEEE 2012)
  13. High-Throughput Efficient Non-Binary LDPC Decoder Based on the Simplified Min-Sum Algorithm(IEEE 2012)
  14. A VLSI Field-Programmable Mixed-Signal Array to Perform Neural Signal Processing and Neural Modeling in a Prosthetic System(IEEE 2012)
  15. A Non Linear Equation Based Cryptosystem for Image Encryption and Decryption(IEEE 2012)
  16. VLSI Design and Implementation of Homophonic Security System(IEEE 2012)
  17. Subband coding for large-scale scientific simulation data using JPEG 2000(IEEE 2012)
  18. Memory Efficient Modular VLSI Architecture for Highthroughput and Low-Latency Implementation of Multilevel Lifting 2-D DWT (IEEE 2011)
  19. An Efficient Implementation of Floating Point Multiplie r(IEEE 2011)
  20. VLSI Realization of a Secure Cryptosystem for Image Encryption and Decryption (IEEE 2011)
  21. Cell-Based VLSI Implementations of the Add One Carry Select Adder (IEEE 2011)
  22. Time-Multiplexed Online Checking (IEEE 2011)
  23. Low-Error and Hardware-Efficient Fixed-Width Multiplier by Using the Dual-Group Minor Input Correction Vector to Lower Input Correction Vector Compensation Error (IEEE 2011)
  24. VLSI Realization of a Secure Cryptosystem for Image Encryption and Decryption (IEEE 2011)
  25. Time-Multiplexed Online Checking (IEEE 2011)
  26. THE KEY EXCHANGE CRYPTOSYSTEM USED WITH HIGHER ORDER DIOPHANTINE EQUATIONS (IEEE 2011)
  27. Memory Efficient Modular VLSI Architecture for Highthroughput and Low-Latency Implementation of Multilevel Lifting 2-D DWT (IEEE 2011)
  28. Performance Analysis of Integer Wavelet Transform for Image Compression (IEEE 2011)
  29. Cell-Based VLSI Implementations of the Add One Carry Select Adder (IEEE 2011)
  30. Performance of MIMO-OFDMA Systems in Correlated Fading Channels and Non-Stationary Interference (IEEE 2011)
  31. Design and Implementation of Low Power Digital FIR Filter based on low power multipliers and adders on xilinx FPGA (IEEE 2011)
  32. Design and Characterization of Parallel Prefix Adders using FPGAs (IEEE 2011)
  33. VHDL environment for floating point Arithmetic Logic Unit - ALU design and simulation (IEEE 2011)
  34. A Novel VLSI Architecture for Low power FIR Filter (IEEE 2011)
  35. Implementation of Floating Point Divider for Interval Arithmetic (IEEE 2011)
  36. Improved Tolerance based Selective Arithmetic Mean Filter for Detection and Removal of Impulse Noise (IEEE 2010)
  37. Area-Efficient Parallel FIR Digital Filter Structures for Symmetric Convolutions Based on Fast FIR Algorithm (IEEE 2010)
  38. Real-Time Perceptual Watermarking Architectures for Video Broadcasting (IEEE 2010)
  39. Implementation of Energy Efficient Integer Wavelet Transform in Spartan 3E FPGA (IEEE 2010)
  40. Dual Stack Method: A Novel Approach to Low Leakage and Speed Power Product VLSI Design (IEEE 2010)
  41. Parallel FPGA-based Implementation of Recursive Sorting Algorithms (IEEE 2010)
  42. A New Algorithm of Encryption and Decryption of Images Using Chaotic Mapping Moving Object Detection in Spatial Domain using Background Removal Techniques – State-of-Art (IEEE 2008)
  43. FAULT TOLERANT METHODS FOR RELIABILITY IN FPGAs (IEEE 2008)
  44. A Five-Stage Pipeline, 204 Cycles/MB, Single-Port SRAM-Based Deblocking Filter for H.264/AVC (IEEE 2008)
  45. THE SELECTION OF REVERSIBLE INTEGER-TO-INTEGER WAVELET TRANSFORMS FOR DEM MULTI-SCALE REPRESENTATION AND PROGRESSIVE COMPRESSION (IEEE 2008)
  46. System Architecture and Implementation of MIMO Sphere Decoders on FPGA (IEEE 2008)
  47. An Overview of Image Compression Approaches (IEEE 2008)
  48. Exploitation of the External JTAG Interface for Internally Controlled Configuration
  49. Readback and Self-Reconfiguration of Spartan 3 FPGAs (IEEE 2008)
  50. FPGA Based Implementation of Robust Watermarking System (IEEE 2008)
  51. FPGA Design of Fast Lifting Wavelet Transform (IEEE 2008)
  52. FPGA Implementation of an 8-bit Simple Processor (IEEE 2008)
  53. A LOW COST FPGA BASED USB DEVICE CORE (IEEE 2008)
  54. FPGA Hardware Architecture of the Steganographic ConText Technique (IEEE 2008)
  55. Embedded into an FPGA (IEEE 2008)
  56. Component Labeling for k-Concave Binary Images Using an FPGA (IEEE 2008)
  57. FPGA BASED IMPLEMENTATION OF ADAPTIVE MEDIAN FILTER (IEEE 2008)
  58. FPGA BASED IMPLEMENTATION OF ROBUST WATER MARKING SYSTEM (IEEE 2008)
  59. FPGA BASED SYSTEM DESIGN SUITABLE FOR ZIGBEE BASED HEALTH MONITORING SYSTEM (IEEE 2008 )
  60. Color Histogram Features Based Image Classification in Content-Based Image Retrieval Systems (IEEE 2008)
  61. A J2ME-Based Wireless Intelligent Video Surveillance System Using Moving Object Recognition Technology (IEEE 2008)
  62. System's Design and Implementation for Easy Creation of Mobile Commerce Systems (IEEE 2008)
  63. Automatic Generation of Web User Interfaces Using Database Metadata (IEEE 2008)
  64. Personal Authentication Based on Iris Texture Analysis (IEEE 2008)
  65. Public Key-embedded Graphic CAPTCHAs (IEEE 2008)
  66. Intelligent Heart Disease Prediction System Using Data Mining Techniques (IEEE 2008)
  67. A Fuzzy Similarity Approach for Automated Spam Filtering (IEEE 2008)
  68. Employing Bayes Classifier for Improving Learner's Proficiency (IEEE 2008)
  69. Real-Time ECG Monitoring System Based on FPGA (IEEE 2007)
  70. Real-time Object Boundary Tracing Circuit Based on FPGA (IEEE 2007)
  71. Security in SRAM FPGAs (IEEE 2007)
  72. SEQUENTIAL, IRREGULAR AND COMPLEX OBJECT CONTOUR TRACING ON FPGA (IEEE 2007)
  73. Real time and Robust Motion Tracking by Matched Filter on CMOS+FPGA
  74. FPGA BASED DESIGN AND VERIFICATION OF BLOWFISH ALGORITHM
  75. Real-time Component Labeling and Boundary Tracing System Based on FPGA (IEEE 2007)
  76. A Pipelined Reconfigurable Architecture for Real-time Image Processing of Robot Vision Servoing (IEEE 2007)
  77. Performance Evaluation of FPGA -Embedded Web Servers (IEEE 2007)
  78. An Open-loop Stepper Motor Driver Based on FPGA (IEEE 2007)
  79. Online Monitoring and Remote FPGA Configuration Using JTAG Over Ethernet (IEEE 2007)
  80. MicroBlaze based Image Processing System using IEEE1394a (IEEE 2007)
  81. K-means Clustering for Multispectral Images Using Floating-Point Divide (IEEE 2007)
  82. Implementation of a Multi-channel UART Controller Based on FIFO Technique and FPGA (IEEE 2007)
  83. Implementation and Evaluation of a High Speed License Plate Recognition System on an FPGA (IEEE 2007)
  84. Hardware modeling and implementation of modified SPIHT algorithm for compression of images (IEEE 2007)
  85. FPGA BASED DESIGN AND VERIFICATION OF IMAGE FUSION
  86. FPGAImplementation of Neural Nonlinear ADCbased Temperature Measurement System (IEEE 2007)
  87. FPGA Implementation of an Efficient 3D-WT Temporal Decomposition Algorithm for Video Compression (IEEE 2007)
  88. FPGA Implementation of 3D Discrete Wavelet Transform for Real-Time Medical Imaging (IEEE 2007)
  89. FPGA Design Methodology for Industrial Control Systems—A Review (IEEE 2007)
  90. FPGA Configuration by TCP/IP and Ethernet (IEEE 2007)
  91. FPGA Based System design suitable for Wireless Health Monitoring Employing Intelligent RF module (IEEE 2007)
  92. FPGA BASED REMOTE INTEGRATED SECURITY SYSTEM BASED WAP
  93. An analysis of FPGA-based UDP/IP stack parallelism for embedded Ethernet connectivity (IEEE 2007)
  94. FPGA BASED REAL TIME IMPLEMENTATION OF RF BASED TOLGATE SYSTEM (IEEE 2007)
  95. AN EFFI.CIENT IMPLEMENTATION OF A 2D DWT ON FPGA (IEEE 2007)
  96. AES-128 CIPHER. HIGH SPEED, LOW COST FPGA IMPLEMENTATION (IEEE 2007)
  97. A VLSI Progressive Coding for Waveletbased Image Compression (IEEE 2007)
  98. WEBSERVER BASED ENERGY MEASUREMENT & CONTROLLING
  99. Dynamically Optimizing FPGA Applications by Monitoring Temperature and Workloads (IEEE 2007)
  100. A Real-Time Implementation of Chaotic Contour Tracing and Filling of Video objects on Reconfigurable Hardware (IEEE 2007)
  101. 8-bit AES FPGA Implementation using Block RAM (IEEE 2007)
  102. A HIGH SPEED LICENSE PLATE RECOGNITION SYSTEM ON AN FPGA (IEEE 2007)
  103. THE ELECTRONIC PASSPORT AND THE FUTURE GOVERNMENT ISSSUED RFID BASED IDENTIFICATION (IEEE 2007 )
  104. Haar Wavelet Based Approach for Image Compression and Quality Assessment of Compressed Image (IEEE 2007)
  105. Automatic Design of Area-Efficient Configurable ASIC Cores (IEEE 2007)
  106. Error Correction On-Demand: A Low Power Register Transfer Level Concurrent Error Correction Technique (IEEE 2007)
  107. Improvement of the Orthogonal Code Convolution Capabilities Using FPGA Implementation (IEEE 2007)
  108. Images Using Median Controlled Adaptive Recursive Weighted Median Filter (IEEE 2007)
  109. Design and Implementation of a Memory Controller for Real-Time Applications (EEE2006)
  110. A New Method for Real-Time Steganography (IEEE 2006)
  111. DES Decoding Using FPGA and Custom Instructions (IEEE 2006)
  112. Embedded and Scalable image Coding Based on Virtual SPIlT (IEEE 2006)
  113. FPGA ARCHITECTURE FOR REAL-TIME VIDEO NOISE ESTIMATION (IEEE 2006)
  114. A High-Performance VLSI Architecture for Advanced Encryption Standard (AES) Algorithm (IEEE 2006)
  115. FPGA-Based Real-Time Image Segmentation for Medical Systems and Data Processing (IEEE 2006)
  116. Reconfigurable Implementation of Wavelet based Image Denoising (IEEE 2006)
  117. Image Segmentation and Pattern Matching Based FPGA/ASIC Implementation
  118. Architecture of Real-Time Object Tracking (IEEE 2006)
  119. Speech Recognition for Disabilities People (IEEE 2006)
  120. An FPGA Based General Purpose Data Acquisition Controller (IEEE 2005)
  121. FPGA based Remote Object Tracking for Real-time Control (IEEE 2005)
  122. Fault Tolerance of Switch Blocks and Switch Block Arrays in FPGA (IEEE 2005)
  123. ADAPTIVE WEIGHT GENERATION (IEEE 2005)
  124. An image encryption approach based on chaotic maps (IEEE 2004)
  125. Algorithm Level Recomputing Using Allocation Diversity: A Register Transfer Level Approach to Time Redundancy-Based Concurrent Error Detection (IEEE 2002)
  126. Chaos and Cryptography: Block Encryption Ciphers Based on Chaotic Maps (IEEE 2001)
  127. CONFIGURABLE HARDWARE IMPLEMENTATION OF TRIPLE-DES ENCRYPTION ALGORITHM FOR WIRELESS LOCAL AREA NETWORK (IEEE 2001)
  128. Providing Network Connectivity for Small Appliances: A Functionally Minimized Embedded Web Server (IEEE 2001)
  129. Two-Dimensional CRC for Efficient Transmission of ATM Cells over CDMA (IEEE 2000)
  130. Progressive Switching Median Filter for the Removal of Impulse Noise from Highly Corrupted Images (EEE 1999)
  131. Wavelet Transforms That Map Integers to Integers (IEEE 1998)
  132. A Time-Multiplexed FPGA (IEEE 1997)
  133. Lossless Integer Wavelet Transform (IEEE 1997)
  134. Image Compression Using Wavelet Transform and Multiresolution Decomposition (IEEE 1996)
  135. Pipelined Architecture for FPGA Implementation of Lifting-Based DWT (IEEE 1992)
  136. The Output Distributionof Median Type Filters (IEEE 1984)
  137. High Density Impulse noise Removal in Color
  138. Sleepy Keeper: a New Approach to Low-leakage Power VLSI Design
  139. Generalized Secure Hash Algorithm: SHA-X
  140. Understanding Reliability and Validity in Qualitative Research
  141. INTEGER WAVELET TRANSFORM BASED LOSSLESS AUDIO COMPRESSION
  142. IMAGE ENCRYPTION & DECRYPTION MODEL
  143. Design And Application Guide For High Speed MOSFET Gate Drive Circuits
  144. FPGA IMPLEMENTATION OF VARIANTS OF MIN-SUM ALGORITHM
  145. IMPLEMENTATION OF FAST FOURIER AND INVERSE FAST FOURIER TRANSFORMS IN FPGA
  146. JPEG Encoder for Low-Cost FPGAs
  147. WEBSERVER BASED DATA ACQUSITION SYSTEM
  148. FPGA BASED CRITICAL REAL TIME APPLICATIONS FOR ATM SECURITY SYSTEM.
  149. FPGA BASED AS ID TAG CONTAINING MEDICAL INFORMATION ABOUT THE PATIENT
  150. LIBRARY MANAGEMENT SYSTEM USING ZIGBEE MODULE
  151. RF BASED RAILWAY TRACK DAMAGE NOTIFICATION WITH ALERT
  152. FPGA BASED SYSTEM DESIGN SUITABLE FOR REAL TIME PASSENGER
  153. INFORMATION SYSTEM USING ZIGBEE TECHNOLOGY.
  154. Amplitude Phase Shift Keying Modulator & Demodulator Design using System Generator
  155. Microprocessor and Microcontroller design implementation on FPGA
  156. Frequency domain Filter Implementation for 3G communication.
  157. Implementation of an Embedded GPS Receiver Based on FPGA and Micro Blaze
  158. HWSW Co-Simulation Platforms for VLSI Design
  159. A HW/SW Co-Verification Technique for Field Programmable Gate Array (FPGA) Test
  160. Embedded a low area 32-bit AES for image encryption/decryption application
  161. Designing of VGA Character String Display Module Based on FPGA
  162. Embedded System with uClinux Based on FPGA
  163. Broadband Receiver Design on FPGA
  164. Quadrature Phase Shift Keying Modulator &Demodulator for Wireless Modem
  165. Open-loop stepper motor driver based on FPGA
  166. Position Control of an AC Servo Motor Using VHDL & FPGA
  167. FPGA BASED SPEED CONTROL OF THREE-PHASE INDUCTION MOTOR USING STATOR VOLTAGE REGULATOR
  168. FPGA Based Speed Control of AC Servomotor Using Sinusoidal PWM
  169. FPGA Based Implementation of Space Vector Modulated Direct Torque Control For Induction Motor Drive Control a three-phase full-wave rectifier with an FPGA
  170. Modeling and Simulation of FPGA based direct Torque Control of Induction Motor Drive.
  171. A Pipeline VLSI Architecture for High-Speed Computation of the 1-D Discrete Wavelet Transform
  172. FPGA Implementation of Wavelet Transform Based on Lifting Scheme
  173. High-Speed FPGA Implementation for DWT of Lifting Scheme
  174. Message Encoding in Images Using Lifting Schemes
  175. SPIHT algorithm combined with Huffman encoding
  176. An Efficient VLSI Architecture for Discrete Wavelet Transform based on the Daubechies Architecture
  177. The Lifting Scheme for Wavelet Bi-Frames: Theory, Structure, and Algorithm
  178. An efficient architecture for 2-D lifting-based discrete wavelet transform
  179. Memory-Efficient and High-Speed Line-Based Architecture for 2-D Discrete Wavelet Transform with Lifting Scheme
  180. Discrete Wavelet Transform FPGA Design using MatLab/Simulink
  181. A Framework for FPGA based Discrete Biorthogonal Wavelet Transforms Implementation
  182. AN EFFICIENT BUFFER-BASED ARCHITECTURE FOR ON-LINE COMPUTATION OF 1-D DISCRETE WAVELET TRANSFORM
  183. An Efficient VLSI Architecture and FPGA Implementation of High-Speed and Low Power 2-D DWT for (9, 7) Wavelet Filter
  184. A Rescheduling and Fast Pipeline VLSI Architecture for Lifting-based Discrete Wavelet Transform
  185. High Performance VLSI Architecture of 2D Discrete Wavelet Transform with Scalable Lattice Structure
  186. Reconfigurable VLSI Architecture for 9/7-5/3 Discrete Wavelet Transform
  187. Parallel form of the Pipelined Lifting-based VLSI Architectures for Two-dimensional Discrete Wavelet Transform
  188. An Efficient VLSI Architecture lifting based DWT by systematic design method
  189. Efficient VLSI Architecture for Lifting-Based Discrete Wavelet Packet Transform
  190. High-Efficient Architectures for 2-D Lifting-Based Forward and Inverse Discrete Wavelet Transform
  191. FPGA Realization of Lifting Based Forward Discrete Wavelet Transform for JPEG 2000
  192. Lifting-based VLSI Architectures for Two-Dimensional Discrete Wavelet Transform for Effective Image Compression
  193. Scalable VLSI Architectures for Lattice Structure-Based Discrete Wavelet Transform
  194. Highly Efficient High-Speed/Low-Power Architectures for the 1-D Discrete Wavelet Transform
  195. FPGA DESIGN OF A HARDWARE EFFICIENT PIPELINED FFT PROCESSOR
  196. Efficient FPGA implementation of FFT/IFFT Processor
  197. Design of Pipelined FFT Processor Based on FPGA
  198. FPGA based hybrid accumulator architecture for digital chirp synthesis
  199. Solar Tracking Fuzzy Control System Design using FPGA
  200. Efficient FPGA Design and Implementation of Digital PID Controllers in Simulink®
  201. Efficient Design and Fpga Implementation of Digital Controller Using Xilinx SysGen
  202. FPGA Implementation of Fuzzy Logic Controller For Elevator Group Control System
  203. FPGA-Based Fuzzy Logic: Design and Applications – a Review
  204. FPGA-based Controller for a Mobile Robot
  205. Fail-Safe ECU System Using Dynamic Reconfiguration Of FPGA
  206. A new and efficient algorithm for the removal of high density salt and pepper noise in images and videos
  207. FPGA Implementation of Image Segmentation Processor
  208. VLSI architectures of perceptual based video watermarking for real-time copyright protection
  209. Design of Image Acquisition and Processing Based on FPGA
  210. Research on Image Median Filtering Algorithm and Its FPGA Implementation
  211. High throughput one dimensional median and weighted median filters on FPGA
  212. FPGA based design and verification of image segmentation for medical systems and data Processing
  213. Novel Hardware Implementation of Adaptive Median Filters
  214. An Efficient Hardware Architecture for Multimedia Encryption and Authentication using the Discrete Wavelet Transform
  215. VLSI architectures of perceptual based video watermarking for real-time copyright protection
  216. FPGA Hardware Architecture of the Steganographic ConText Technique
  217. Development of FPGA Based Adaptive Image Enhancement Filter System Using Genetic Algorithms
  218. FPGA Implementation for Image Processing Algorithms
  219. Architecture for filtering images using Xilinx System Generator
  220. A Methodology for Architecture Synthesis of Cascaded IIR Filters on TLU FPGAs
  221. Chebyshev IIR filter sharpening implemented on FPGA
  222. VHDL-MODELS OF PARALLEL FIR DIGITAL FILTERS
  223. FPGA IMPLEMENTATION OF DIGITAL FILTERS
  224. FPGA-Based Digital Filters Using Bit-Serial Arithmetic
  225. High Speed and Low Power FPGA Implementation of FIR Filter for DSP Applications
  226. FPGA-implementation of time-multiplexed multiple constant multiplication based on carry save Arithmetic Hand Gesture Recognition System Based on Associative Processors real time
  227. Design and Development of Activation and Monitoring of Home Automation System via SMS through FPGA
  228. Multi-sensory system for obstacle detection on railways
  229. An Optimized RFID-Based Academic Library
  230. Design and Implement of the Embedded Elevator Monitor System based on Wireless Communication
  231. Bluetooth-GMRS Car Security System with a Randomly Located Movement Detect Device
  232. A Design of Bi-verification Vehicle Access Intelligent Control System Based on RFID
  233. Smart Digital Door Lock for the Home Automation
  234. An Integrated Library Management System for Book Search and Placement Tasks
  235. Design and implementation of mobile based electrical appliances control for industrial Automation
  236. An RFID Based Solution for Real-Time Patient Surveillance and data Processing Bio-Metric System using FPGA
  237. An efficient VLSI implementation of intelligent Airport Security System for secure Trespassing Using Advanced RFID Techniques
  238. RF Based Railway Bridge Damage Notification with Alert using FPGA
  239. Implementation of Tsunami Alert System using FPGA
  240. FPGA based System for Enhancing Medication Safety and Healthcare for Inpatients Using RFID
  241. FPGA based remote integrated security system based WAP(wireless application protocol)
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